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16-bit, 1 msps pulsar adc in msop/qfn ad7980 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007C2009 analog devices, inc. all rights reserved. features 16-bit resolution with no missing codes throughput: 1 msps low power dissipation: 7.0 mw @ 1 msps, 70 w @ 10 ksps inl: 0.6 lsb typical, 1.25 lsb maximum sinad: 91.25 db @ 10 khz thd: ?110 db @ 10 khz pseudo differential analog input range 0 v to v ref with v ref between 2.5 v to 5.5 v any input range and easy to drive with the ada4841 no pipeline delay single-supply 2.5 v operation with 1.8 v/2.5 v/3 v/5 v logic interface serial interface spi-/qspi?-/microwire?-/dsp-compatible daisy-chain multiple adcs and busy indicator 10-lead msop and 10-lead, 3 mm 3 mm, qfn (lfcsp), same space as sot-23 wide operating temperature range: ?40c to +125c applications battery-powered equipment communications ate data acquisitions medical instruments application diagram example ad7980 ref gnd vdd in+ in? vio sdi sck sdo cnv 1.8v to 5v 3- or 4-wire interface (spi, daisy chain, cs) 2.5v to 5 v 2.5 v 0 to vre f 06392-001 figure 1. general description the ad7980 is a 16-bit, successive approximation, analog-to- digital converter (adc) that operates from a single power supply, vdd. it contains a low power, high speed, 16-bit sampling adc and a versatile serial interface port. on the cnv rising edge, it samples an analog input in+ between 0 v to ref with respect to a ground sense in?. the reference voltage, ref, is applied externally and can be set independent of the supply voltage, vdd. its power scales linearly with throughput. the spi-compatible serial interface also features the ability, using the sdi input, to daisy-chain several adcs on a single, 3-wire bus and provides an optional busy indicator. it is compatible with 1.8 v, 2.5 v, 3 v, or 5 v logic, using the separate supply vio. the ad7980 is housed in a 10-lead msop or a 10-lead qfn (lfcsp) with operation specified from ?40c to +125c. table 1. msop, qfn (lfcsp) 14-/16-/18-bit pulsar? adc type 100 ksps 250 ksps 400 ksps to 500 ksps 1000 ksps adc driver 18-bit ad7691 1 ad7690 1 ad7982 1 ada4941 ada4841 16-bit ad7680 ad7685 1 ad7686 1 ad7980 1 ada4941 ad7683 ad7687 1 ad7688 1 ada4841 ad7684 ad7694 ad7693 1 14-bit ad7940 ad7942 1 ad7946 1 1 pin-for-pin compatible.
ad7980 rev. b | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 application diagram example........................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications ....................................................................... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 terminology ...................................................................................... 8 typical performance characteristics ............................................. 9 theory of operation ...................................................................... 13 circuit information .................................................................... 13 converter operation .................................................................. 13 typical connecti on diagram ................................................... 14 analog input ............................................................................... 15 driver amplifier choice ........................................................... 15 voltage reference input ............................................................ 16 power supply ............................................................................... 16 digital interface .......................................................................... 16 cs mode, 3-wire, without busy indicator ............................ 17 cs mode 3-wire with busy indicator ..................................... 18 cs mode 4-wire, without busy indicator ............................. 19 cs mode 4-wire with busy indicator ..................................... 20 chain mode, without busy indicator ..................................... 21 chain mode with busy indicator ............................................. 22 application hints ........................................................................... 23 layout .......................................................................................... 23 evaluating the performance of the ad7980 ............................... 23 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 25 revision history 6/09rev. a to rev. b changes to table 5 ............................................................................ 6 changes to figure 25 ...................................................................... 13 updated outline dimensions ....................................................... 24 changes to ordering guide .......................................................... 25 9/08rev. 0 to rev. a delete qfn endnote ..................................................... throughout changes to ordering guide .......................................................... 24 8/07revision 0: initial version
ad7980 rev. b | page 3 of 28 specifications vdd = 2.5 v, vio = 2.3 v to 5.5 v, v ref = 5 v, t a = C40c to +125c, unless otherwise noted. table 2. a grade b grade parameter conditions min typ max min typ max unit resolution 16 16 bits analog input voltage range in+ ? in? 0 v ref 0 v ref v absolute input voltage in+ ?0.1 v ref + 0.1 ?0.1 v ref + 0.1 v in? ?0.1 +0.1 ?0.1 +0.1 v analog input cmrr f in = 100 khz 60 60 db leakage current @ 25c acquisition phase 1 1 na input impedance see the analog input section see the analog input section accuracy no missing codes 16 16 bits differential linearity error ref = 5 v ?1.0 0.5 +2.0 ?0.9 0.4 +0.9 lsb 1 ref = 2.5 v 0.7 0.55 lsb 1 integral linearity error ref = 5 v ?2.5 1.5 +2.5 ?1.25 0.6 +1.25 lsb 1 ref = 2.5 v 1.65 0.65 lsb 1 transition noise ref = 5 v 0.75 0.6 lsb 1 ref = 2.5 v 1.2 1.0 lsb 1 gain error, t min to t max 2 2 2 lsb 1 gain error temperature drift 0.35 0.35 ppm/c zero error, t min to t max 2 ?1.0 0.08 +1.0 ?0.5 0.08 +0.5 mv zero temperature drift 0.54 0.54 ppm/c power supply sensitivity vdd = 2.5 v ? 5% 0.1 0.1 lsb 1 throughput conversion rate vio 2.3 v up to 85c, vio 3.3 v above 85c up to 125c 0 1 0 1 msps transient response full-scale step 290 290 ns ac accuracy dynamic range v ref = 5 v 91 92 db 3 v ref = 2.5 v 86 87 db 3 oversampled dynamic range f o = 10 ksps 110 111 db 3 signal-to-noise ratio, snr f in = 10 khz, v ref = 5 v 90 90 91 db 3 f in = 10 khz, v ref = 2.5 v 85.5 86.5 db 3 spurious-free dynamic range, sfdr f in = 10 khz ?103.5 ?110 db 3 total harmonic distortion, thd f in = 10 khz ?101 ?114 db 3 signal-to-(noise + distortion), sinad f in = 10 khz, v ref = 5 v 90.5 91.5 db 3 f in = 10 khz, v ref = 2.5 v 86.0 87.0 db 3 1 lsb means least significant bit. with the 5 v input range, 1 lsb is 76.3 v. 2 see the terminology section. these specif ications include full temperature range va riation, but not the error contribution fro m the external reference. 3 all specifications in db are referred to a full-scale input fsr. tested with an input signal at 0.5 db below full scale, unles s otherwise specified.
ad7980 rev. b | page 4 of 28 vdd = 2.5 v, vio = 2.3 v to 5.5 v, v ref = 5 v, t a = C40c to +125c, unless otherwise noted. table 3. parameter conditions min typ max unit reference voltage range 2.4 5.1 v load current 1 msps, ref = 5 v 330 a sampling dynamics ?3 db input bandwidth 10 mhz aperture delay vdd = 2.5 v 2.0 ns digital inputs logic levels v il vio > 3v C0.3 0.3 vio v v ih vio > 3v 0.7 vio vio + 0.3 v v il vio 3v C0.3 0.1 vio v ih vio 3v 0.9 vio vio + 0.3 a i il ?1 +1 a i ih ?1 +1 a digital outputs data format serial 16 bits straight binary pipeline delay conversion results available immediately after completed conversion v ol i sink = 500 a 0.4 v v oh i source = ?500 a vio ? 0.3 v power supplies vdd 2.375 2.5 2.625 v vio specified performance 2.3 5.5 v vio range 1.8 5.5 v standby current 1, 2 vdd and vio = 2.5 v, 25c 0.35 na power dissipation 10 ksps throughput 70 w 1 msps throughput, b grade 7.0 9.0 mw 1 msps throughput, a grade 7.0 10 mw energy per conversion 7.0 nj/sample temperature range 3 specified performance t min to t max ?40 +125 c 1 with all digital inputs forced to vio or gnd as required. 2 during the acquisition phase. 3 contact sales for extended temperature range.
ad7980 rev. b | page 5 of 28 timing specifications ?40c to +125c, vdd = 2.37 v to 2.63 v, vio = 3.3 v to 5.5 v, unless otherwise stated. see figure 2 and figure 3 for load cond itions. table 4. parameter symbol min typ max unit conversion time: cnv rising edge to data available t conv 500 710 ns acquisition time t acq 290 ns time between conversions t cyc 1000 ns cnv pulse width (cs mode) t cnvh 10 ns sck period (cs mode) t sck ns vio above 4.5 v 10.5 ns vio above 3 v 12 ns vio above 2.7 v 13 ns vio above 2.3 v 15 ns sck period (chain mode) t sck ns vio above 4.5 v 11.5 ns vio above 3 v 13 ns vio above 2.7 v 14 ns vio above 2.3 v 16 ns sck low time t sckl 4.5 ns sck high time t sckh 4.5 ns sck falling edge to data remains valid t hsdo 3 ns sck falling edge to data valid delay t dsdo vio above 4.5 v 9.5 ns vio above 3 v 11 ns vio above 2.7 v 12 ns vio above 2.3 v 14 ns cnv or sdi low to sdo d15 msb valid (cs mode) t en vio above 3 v 10 ns vio above 2.3 v 15 ns cnv or sdi high or last sck falling edge to sdo high impedance (cs mode) t dis 20 ns sdi valid setup time from cnv rising edge t ssdicnv 5 ns sdi valid hold time from cnv rising edge (cs mode) t hsdicnv 2 ns sdi valid hold time from cnv rising edge (chain mode) t hsdicnv 0 ns sck valid setup time from cnv rising edge (chain mode) t ssckcnv 5 ns sck valid hold time from cnv rising edge (chain mode) t hsckcnv 5 ns sdi valid setup time from sck falling edge (chain mode) t ssdisck 2 ns sdi valid hold time from sck falling edge (chain mode) t hsdisck 3 ns sdi high to sdo high (chain mode with busy indicator) t dsdosdi 15 ns 500a i ol 500a i oh 1.4v to sdo c l 20pf 06513-002 figure 2. load circuit fo r digital interface timing 06392-003 x% vio 1 y% vio 1 v ih 2 v il 2 v il 2 v ih 2 t delay t delay 1 for vio 3.0v, x = 90 and y = 10; for vio > 3.0v x = 70, and y = 30. 2 minimum v ih and maximum v il used. see digital inputs specifications in table 3. figure 3. voltage levels for timing
ad7980 rev. b | page 6 of 28 absolute maximum ratings table 5. parameter rating analog inputs in+, 1 in? 1 to gnd ?0.3 v to v ref + 0.3 v or 130 ma supply voltage ref, vio to gnd ?0.3 v to +6 v vdd to gnd ?0.3 v to +3 v vdd to vio +3 v to ?6 v digital inputs to gnd ?0.3 v to vio + 0.3 v digital outputs to gnd ?0.3 v to vio + 0.3 v storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance (10-lead msop) 200c/w jc thermal impedance (10-lead msop) 44c/w lead temperature vapor phase (60 sec) 215c infrared (15 sec) 220c 1 see the analog input section. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad7980 rev. b | page 7 of 28 pin configurations and function descriptions 06392-004 ref 1 vdd 2 in+ 3 in? 4 vio 10 sdi 9 sck 8 sdo 7 gnd 5 cnv 6 ad7980 top view (not to scale) figure 4. 10-lead msop pin configuration 06392-005 ref 1 vdd 2 in+ 3 in? 4 10 vio 9 sdi 8 sck 7 sdo gnd 5 6 cnv ad7980 top view (not to scale) figure 5. 10-lead qfn (lfcsp) pin configuration table 6. pin function descriptions pin no. mnemonic type 1 description 1 ref ai reference input voltage. the ref range is from 2.4 v to 5.1 v. it is referred to the gnd pin. this pin should be decoupled closely to the pin with a 10 f capacitor. 2 vdd p power supply. 3 in+ ai analog input. it is referred to in?. the voltage range, for example, the difference between in+ and in?, is 0 v to v ref . 4 in? ai analog input ground sense. to be connected to the analog ground plane or to a remote sense ground. 5 gnd p power supply ground. 6 cnv di convert input. this input has multiple functions. on its leading edge, it initiates the conversions and selects the interface mode of the part, chain, or cs mode. in cs mode, it enables the sdo pin when low. in chain mode, the data should be read when cnv is high. 7 sdo do serial data output. the conversion result is output on this pin. it is synchronized to sck. 8 sck di serial data clock input. when the part is select ed, the conversion result is shifted out by this clock. 9 sdi di serial data input. this input provides multiple fe atures. it selects the interface mode of the adc as follows. chain mode is selected if sdi is low during the cnv rising edge. in this mode, sdi is used as a data input to daisy-chain the conversion results of two or more adcs onto a single sdo line. the digital data level on sdi is output on sdo with a delay of 16 sck cycles. cs mode is selected if sdi is high during the cnv rising edge. in this mode, either sdi or cnv can enable the serial output signals when low; if sdi or cnv is low when the conversion is complete, the busy indicator feature is enabled. 10 vio p input/output interface digital power. nominally at the sa me supply as the host interface (1.8 v, 2.5 v, 3 v, or 5 v). 1 ai = analog input, di = digital input, do = digital output, and p = power.
ad7980 rev. b | page 8 of 28 terminology integral nonlinearity error (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line (see figure 26). differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. offset error the first transition should occur at a level ? lsb above analog ground (38.1 v for the 0 v to 5 v range). the offset error is the deviation of the actual transition from that point. gain error the last transition (from 111 10 to 111 11) should occur for an analog voltage 1? lsb below the nominal full scale (4.999886 v for the 0 v to 5 v range). the gain error is the deviation of the actual level of the last transition from the ideal level after the offset is adjusted out. spurious-free dynamic range (sfdr) sfdr is the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad by the following formula enob = ( sinad db ? 1.76)/6.02 and is expressed in bits. noise-free code resolution noise-free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. it is calculated as noise-free code resolution = log 2 (2 n / peak-to-peak noise ) and is expressed in bits. effective resolution effective resolution is calculated as effective resolution = log 2 (2 n / rms input noise ) and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in db. dynamic range dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. the value for dynamic range is expressed in db. it is measured with a signal at ?60 dbfs to include all noise sources and dnl artifacts. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in db. signal-to-(noise + distortion) ratio (sinad) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in db. aperture delay aperture delay is the measure of the acquisition performance. it is the time between the rising edge of the cnv input and when the input signal is held for a conversion. transient resp onse transient response is the time required for the adc to accurately acquire its input after a full-scale step function is applied.
ad7980 rev. b | page 9 of 28 typical performance characteristics vdd = 2.5 v, v ref = 5.0 v, vio = 3.3 v, unless otherwise noted. 1.25 ?1.25 0 65536 06392-036 code inl (lsb) 1.00 0.75 0.50 0.25 ?0.25 ?0.75 0 ?0.50 ?1.00 16384 32768 49152 positive inl: +0.33 lsb negative inl: ?0.39 lsb figure 6. integral nonlinearity vs. code, ref = 5 v 1.25 1.00 ?1.25 ?1.00 0 65536 06392-060 code inl (lsb) 0.75 0.50 0.25 ?0.25 ?0.75 0 ?0.50 16384 32768 49152 positive inl: +0.47 lsb negative inl: ?0.26 lsb figure 7. integral nonlinearity vs. code, ref = 2.5 v 0 ?180 05 0 0 06392-038 frequency (khz) amplitude (db of full scale) ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 100 200 300 400 f s = 1 msps f in = 10khz snr = 91.27db thd = ?114.63db sfdr = 110.10db sinad = 91.25db figure 8. fft plot, ref = 5 v 1.00 ?1.00 0 65536 06392-039 code dnl (lsb) 0.75 0.50 0.25 ?0.25 ?0.75 0 ?0.50 16384 32768 49152 positive inl: +0.18 lsb negative inl: ?0.21 lsb figure 9. differential nonlinearity vs. code, ref = 5 v 1.00 ?1.00 0 65536 06392-061 code dnl (lsb) 0.75 0.50 0.25 ?0.25 ?0.75 0 ?0.50 16384 32768 49152 positive inl: +0.25 lsb negative inl: ?0.22 lsb figure 10. differential nonlinearity vs. code, ref = 2.5 v 0 ?180 05 0 0 06392-058 frequency (khz) amplitude (db of full scale) ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 100 200 300 400 f s = 1 msps f in = 10khz snr = 86.8db thd = ?111.4db sfdr = 105.9db sinad = 86.8db figure 11. fft plot, ref = 2.5 v
ad7980 rev. b | page 10 of 28 180k 0 800c 800d 800e 800f 80098008 800b 800a 8003 80058004 80078006 2000 33829 0 27 0 1201 06392-042 code in hex counts 140k 160k 100k 120k 60k 20k 80k 40k 38751 168591 52710 figure 12. histogram of a dc input at the code center, ref = 5 v 70k 0 7fff 8008 8001 8000 8003 8002 8005 8004 8007 8006 0 0 150 2 59691 5428 59404 3 93 06392-043 code in hex counts 60k 50k 30k 10k 40k 20k 6295 figure 13. histogram of a dc input at the code transition, ref = 5 v 100 80 85 90 95 2.25 5.25 06392-044 reference voltage (v) snr, sinad (db) 16 12 13 14 15 enob (bits) 2.75 3.25 3.75 4.25 4.75 snr sinad enob figure 14. snr, sinad, and enob vs. reference voltage 60k 0 7ffa 8006 7ffc 7ffb 7ffe 7fff 7ffd 80018000 8003 8004 8005 8002 00 0 0 539 16 14 502 06392-059 code in hex counts 50k 30k 10k 40k 20k 32417 52212 31340 7225 6807 figure 15. histogram of a dc input at the code center, ref = 2.5 v 95 85 87 89 92 91 93 94 86 88 90 ?10 0 06392-046 input level (db of full scale) snr (db) ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 figure 16. snr vs. input level ? 95 ?125 ?110 ?115 ?105 ?100 ?120 115 85 100 95 105 110 90 2.25 5.25 06392-047 reference voltage (v) thd (db) sfdr (db) 2.75 3.25 3.75 4.25 4.75 thd sfdr figure 17. thd, sfdr vs. reference voltage
ad7980 rev. b | page 11 of 28 100 80 10 1000 06392-063 frequency (khz) sinad (db) 95 90 85 100 figure 18. sinad vs. frequency 95 85 89 87 91 93 ?55 125 06392-049 temperature (c) snr (db) ?35 ?15 5 25 65 85 45 105 figure 19. snr vs. temperature 06392-050 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 current (ma) 2.425 2.475 vdd voltage (v) 2.375 2.525 2.575 2.625 i vdd i ref i vio figure 20. operating currents vs. supply ? 85 ?125 10 1000 06392-064 frequency (khz) thd (db) 100 ?90 ?95 ?100 ?105 ?110 ?115 ?120 figure 21. thd vs. frequency 06392-052 ? 110 ?120 thd (db) ?55 ?35 ?15 5 25 temperature (c) 45 65 85 105 125 ?112 ?114 ?116 ?118 figure 22. thd vs. temperature 06392-053 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 current (ma) ?55 ?35 ?15 5 25 temperature (c) 45 65 85 105 125 i vdd i ref i vio figure 23. operating currents vs. temperature
ad7980 rev. b | page 12 of 28 06392-054 8 7 6 5 4 3 2 1 0 current (a) ?55 ?35 ?15 5 25 temperature (c) 45 65 85 105 125 i vdd + i vio figure 24. power-down currents vs. temperature
ad7980 rev. b | page 13 of 28 theory of operation 06392-011 comp switches control busy output code cnv control logic sw+ lsb sw+ lsb in + ref gnd in? msb msb c c 4c 2c 16,384c 32,768c c c 4c 2c 16,384c 32,768c figure 25. adc simplified schematic circuit information the ad7980 is a fast, low power, single-supply, precise 16-bit adc that uses a successive approximation architecture. the ad7980 is capable of converting 1,000,000 samples per second (1 msps) and powers down between conversions. when operating at 10 ksps, for example, it consumes 70 w typically, ideal for battery-powered applications. the ad7980 provides the user with on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed channel applications. the ad7980 can be interfaced to any 1.8 v to 5 v digital logic family. it is housed in a 10-lead msop or a tiny 10-lead qfn (lfcsp) that combines space savings and allows flexible configurations. it is pin-for-pin compatible with the 18-bit ad7982 . converter operation the ad7980 is a successive approximation adc based on a charge redistribution dac. figure 25 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 16 binary weighted capacitors, which are connected to the two comparator inputs. during the acquisition phase, terminals of the array tied to the comparators input are connected to gnd via sw+ and sw?. all independent switches are connected to the analog inputs. therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the in+ and in? inputs. when the acquisition phase is completed and the cnv input goes high, a conversion phase is initiated. when the conversion phase begins, sw+ and sw? are opened first. the two capacitor arrays are then disconnected from the inputs and connected to the gnd input. therefore, the differential voltage between the inputs in+ and in? captured at the end of the acquisition phase are applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between gnd and ref, the comparator input varies by binary weighted voltage steps (v ref /2, v ref /4 v ref /65,536). the control logic toggles these switches, starting with the msb, to bring the comparator back into a balanced condition. after the completion of this process, the part returns to the acquisition phase and the control logic generates the adc output code and a busy signal indicator. because the ad7980 has an on-board conversion clock, the serial clock, sck, is not required for the conversion process.
ad7980 rev. b | page 14 of 28 transfer functions the ideal transfer characteristic for the ad7980 is shown in figure 26 and table 7. 000 ... 000 000 ... 001 000 ... 010 111 ... 101 111 ... 110 111 ... 111 ?fsr ?fsr + 1lsb ?fsr + 0.5lsb +fsr ? 1 lsb +fsr ? 1.5 lsb 0 6392-012 analog input adc code (straight binary) figure 26. adc ideal transfer function table 7. output codes and ideal input voltages analog input description v ref 5 v digital output code (hea) fsr C 1 lsb 4.999924 v ffff 1 midscale + 1 lsb 2.500076 v 8001 midscale 2.5 v 8000 midscale C 1 lsb 2.499924 v 7fff Cfsr + 1 lsb 76.3 v 0001 Cfsr 0 v 0000 2 1 this is also the code for an overranged analog input (v in+ ? v in? above v ref ? v gnd ). 2 this is also the code for an underranged analog input (v in+ ? v in? below v gnd ). tpical connection diaram figure 27 shows an example of the recommended connection diagram for the ad7980 when multiple supplies are available. 06392-013 ad7980 3- or 4-wire interface 2.5v v+ 20? v+ v? 0 to vre f 1.8v to 5v 100nf 10f 2 2.7nf 4 100nf ref in+ in? vdd vio sdi cnv sck sdo gnd ref 1 1 see the voltage reference input section for reference selection. 2 c ref is usually a 10f ceramic capacitor (x5r). 3 see the driver amplifier choice section. 4 optional filter. see the analog input section. 5 see the digital interface for the most convenient interface mode. figure 27. typical application diagram with multiple supplies
ad7980 rev. b | page 15 of 28 analog input figure 28 shows an equivalent circuit of the input structure of the ad7980. the two diodes, d1 and d2, provide esd protection for the analog inputs, in+ and in?. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 v, because this causes these diodes to become forward- biased and start conducting current. these diodes can handle a forward-biased current of 130 ma maximum. for instance, these conditions could eventually occur when the input buffers (u1) supplies are different from vdd. in such a case (for example, an input buffer with a short circuit), the current limitation can be used to protect the part. 06392-014 ref r in c in in+ o r in? gnd d2 c pin d1 figure 28. equivalent analog input circuit the analog input structure allows the sampling of the true differential signal between in+ and in?. by using these differential inputs, signals common to both inputs are rejected. during the acquisition phase, the impedance of the analog inputs (in+ and in?) can be modeled as a parallel combination of capacitor, c pin , and the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 400 and is a lumped component made up of some serial resistors and the on resistance of the switches. c in is typically 30 pf and is mainly the adc sampling capacitor. during the conversion phase, where the switches are opened, the input impedance is limited to c pin . r in and c in make a 1-pole, low-pass filter that reduces undesirable aliasing effects and limits the noise. when the source impedance of the driving circuit is low, the ad7980 can be driven directly. large source impedances significantly affect the ac performance, especially thd. the dc performances are less sensitive to the input impedance. the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades as a function of the source impedance and the maximum input frequency. driver amplifier choice although the ad7980 is easy to drive, the driver amplifier needs to meet the following requirements: ? the noise generated by the driver amplifier needs to be kept as low as possible to preserve the snr and transition noise performance of the ad7980. the noise coming from the driver is filtered by the ad7980 analog input circuits 1-pole, low-pass filter made by r in and c in or by the external filter, if one is used. because the typical noise of the ad7980 is 47.3 v rms, the snr degradation due to the amplifier is ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 3db 2 )( 2 47.3 47.3 log20 n loss nef snr where: f C3db is the input bandwidth in mhz of the ad7980 (10 mhz) or the cutoff frequency of the input filter, if one is used. n is the noise gain of the amplifier (for example, 1 in buffer configuration). e n is the equivalent input noise voltage of the op amp, in nv/hz. ? for ac applications, the driver should have a thd performance commensurate with the ad7980. ? for multichannel multiplexed applications, the driver amplifier and the ad7980 analog input circuit must settle for a full-scale step onto the capacitor array at a 16-bit level (0.0015%, 15 ppm). in the amplifiers data sheet, settling at 0.1% to 0.01% is more commonly specified. this could differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection. table 8. recommended driver amplifiers amplifier typical application ada4841 very low noise, small and low power ad8021 very low noise and high frequency ad8022 low noise and high frequency op184 low power, low noise, and low frequency ad8655 5 v single-supply, low noise ad8605, ad8615 5 v single-supply, low power
ad7980 rev. b | page 16 of 28 voltage reference input the ad7980 voltage reference input, ref, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the ref and gnd pins, as explained in the layout section. when ref is driven by a very low impedance source, for example, a reference buffer using the ad8031 or the ad8605 , a ceramic chip capacitor is appropriate for optimum performance. if an unbuffered reference voltage is used, the decoupling value depends on the reference used. for instance, a 22 f (x5r, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift adr43x reference. if desired, a reference-decoupling capacitor value as small as 2.2 f can be used with a minimal impact on performance, especially dnl. regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nf) between the ref and gnd pins. power supply the ad7980 uses two power supply pins: a core supply, vdd, and a digital input/output interface supply, vio. vio allows direct interface with any logic between 1.8 v and 5.0 v. to reduce the number of supplies needed, vio and vdd can be tied together. the ad7980 is independent of power supply sequencing between vio and vdd. additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in figure 29. 80 55 11000 06392-062 frequency (khz) psrr (db) 10 100 75 70 65 60 figure 29. psrr vs. frequency to ensure optimum performance, vdd should be roughly half of ref, the voltage reference input. for example, if ref is 5.0 v, vdd should be set to 2.5 v (5%). the ad7980 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate. this makes the part ideal for low sampling rate (even of a few hz) and low battery-powered applications. 06392-055 10.000 1.000 0.100 0.010 0.001 oper a ting currents (ma) 100000 sampling rate (sps) 10000 1000000 i vdd i vio i ref figure 30. operating cu rrents vs. sampling rate digital interface though the ad7980 has a reduced number of pins, it offers flexibility in its serial interface modes. the ad7980, when in cs mode, is compatible with spi, qspi, and digital hosts. this interface can use either a 3-wire or 4-wire interface. a 3-wire interface using the cnv, sck, and sdo signals minimizes wiring connections useful, for instance, in isolated applications. a 4-wire interface using the sdi, cnv, sck, and sdo signals allows cnv, which initiates the conversions, to be independent of the readback timing (sdi). this is useful in low jitter sampling or simultaneous sampling applications. the ad7980, when in chain mode, provides a daisy-chain feature using the sdi input for cascading multiple adcs on a single data line similar to a shift register. the mode in which the part operates depends on the sdi level when the cnv rising edge occurs. the cs mode is selected if sdi is high, and the chain mode is selected if sdi is low. the sdi hold time is such that when sdi and cnv are connected together, the chain mode is selected. in either mode, the ad7980 offers the flexibility to optionally force a start bit in front of the data bits. this start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. the busy indicator feature is enabled ? in the cs mode if cnv or sdi is low when the adc conversion ends (see figure 34 and figure 38). ? in the chain mode if sck is high during the cnv rising edge (see figure 42).
ad7980 rev. b | page 17 of 28 cs mode, 3-wire, without busy indicator this mode is usually used when a single ad7980 is connected to an spi-compatible digital host. the connection diagram is shown in figure 31, and the corresponding timing is given in figure 32. with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. once a conversion is initiated, it continues until completion irrespective of the state of cnv. this can be useful, for instance, to bring cnv low to select other spi devices, such as analog multiplexers; however, cnv must be returned high before the minimum conversion time elapses and then held high for the maximum conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the ad7980 enters the acquisition phase and powers down. when cnv goes low, the msb is output onto sdo. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate provided that it has an acceptable hold time. after the 16th sck falling edge or when cnv goes high, whichever is earlier, sdo returns to high impedance. 06392-015 ad7980 sdo sdi data in digital host convert clk vio cnv sck figure 31. 3-wire cs mode without busy indicator connection diagram (sdi high) 06392-016 sdi=1 t cnvh t conv t cyc cnv a quisition aquisition t acq t sck t sckl conversion sck sdo d15 d14 d13 d1 d0 t en t hsdo 123 14 1516 t dsdo t dis t sckh figure 32. 3-wire cs mode without busy indicator seri al interface timing (sdi high)
ad7980 rev. b | page 18 of 28 cs mode 3-wire with busy indicator this mode is usually used when a single ad7980 is connected to an spi-compatible digital host having an interrupt input. the connection diagram is shown in figure 33, and the corresponding timing is given in figure 34. with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. sdo is maintained in high impedance until the completion of the conversion irrespective of the state of cnv. prior to the minimum conversion time, cnv can be used to select other spi devices, such as analog multiplexers, but cnv must be returned low before the minimum conversion time elapses and then held low for the maximum conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low. with a pull-up on the sdo line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. the ad7980 then enters the acquisition phase and powers down. the data bits are clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate provided it has an acceptable hold time. after the optional 17th sck falling edge or when cnv goes high, whichever is earlier, sdo returns to high impedance. if multiple ad7980s are selected at the same time, the sdo output pin handles this contention without damage or induced latch-up. meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. 06392-017 ad7980 sdo sdi data in irq digital host convert clk vio vio 47k? cnv sck figure 33. 3-wire cs mode with bu sy indicator connection diagram (sdi high) 06392-018 t conv t cnvh t cyc aquisition aquisition t acq t sck t sckh t sckl conversion sck cnv sdi = 1 sdo d15 d14 d1 d0 t hsdo 123 15 1617 t dsdo t dis figure 34. 3-wire cs mode with busy indi cator serial interface timing (sdi high)
ad7980 rev. b | page 19 of 28 cs mode 4-wire, without busy indicator this mode is usually used when multiple ad7980s are connected to an spi-compatible digital host. a connection diagram example using two ad7980s is shown in figure 35, and the corresponding timing is given in figure 36. with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback (if sdi and cnv are low, sdo is driven low). prior to the minimum conversion time, sdi can be used to select other spi devices, such as analog multiplexers, but sdi must be returned high before the minimum conversion time elapses and then held high for the maximum conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the ad7980 enters the acquisition phase and powers down. each adc result can be read by bringing its sdi input low, which consequently outputs the msb onto sdo. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate provided it has an acceptable hold time. after the 16th sck falling edge or when sdi goes high, whichever is earlier, sdo returns to high impedance and another ad7980 can be read. 06392-019 digital host convert cs2 cs1 clk data in ad7980 sdo sdi cnv sck ad7980 sdo sdi cnv sck figure 35. 4-wire cs mode without busy indicator connection diagram 06392-020 t conv t cyc aquisition aquisition t acq t sck t sckh t sckl conversion sck cnv t ssdicnv t hsdicnv sdo d15 d13 d14 d1 d0 d15 d14 d1 d0 t hsdo t en 1 2 3 14 15 16 17 18 30 31 32 t dsdo t dis sdi(cs1) sdi(cs2) figure 36. 4-wire cs mode without busy indicato r serial interface timing
ad7980 rev. b | page 20 of 28 cs mode 4-wire with busy indicator this mode is usually used when a single ad7980 is connected to an spi-compatible digital host that has an interrupt input, and it is desired to keep cnv, which is used to sample the analog input, independent of the signal used to select the data reading. this requirement is particularly important in applications where low jitter on cnv is desired. the connection diagram is shown in figure 37, and the corresponding timing is given in figure 38. with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback (if sdi and cnv are low, sdo is driven low). prior to the minimum conversion time, sdi can be used to select other spi devices, such as analog multiplexers, but sdi must be returned low before the minimum conversion time elapses and then held low for the maximum conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low. with a pull-up on the sdo line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. the ad7980 then enters the acquisition phase and powers down. the data bits are clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate provided it has an acceptable hold time. after the optional 17th sck falling edge or sdi going high, whichever is earlier, the sdo returns to high impedance. 06392-021 ad7980 sdo sdi data in irq digital host convert cs1 clk vio 47k ? cnv sck figure 37. 4-wire cs mode with busy indi cator connection diagram 06392-022 t conv t cyc aquisition t ssdicnv aquisition t acq t sck t sckh t sckl conversion sdi t hsdicnv sck cnv sdo t en d15 d14 d1 d0 t hsdo 123 15 1617 t dsdo t dis figure 38. 4-wire cs mode with busy indicator serial interface timing
ad7980 rev. b | page 21 of 28 chain mode, without busy indicator this mode can be used to daisy-chain multiple ad7980s on a 3-wire serial interface. this feature is useful for reducing component count and wiring connections, for example, in isolated multi-converter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using two ad7980s is shown in figure 39, and the corresponding timing is given in figure 40. when sdi and cnv are low, sdo is driven low. with sck low, a rising edge on cnv initiates a conversion, selects the chain mode, and disables the busy indicator. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when the conversion is complete, the msb is output onto sdo and the ad7980 enters the acquisition phase and powers down. the remaining data bits stored in the internal shift register are clocked by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 16 n clocks are required to readback the n adcs. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate and, consequently, more ad7980s in the chain, provided the digital host has an acceptable hold time. the maximum conversion rate may be reduced due to the total readback time. 06392-023 digital host convert clk data in ad7980 sdo sdi cnv a sck ad7980 sdo sdi cnv b sck figure 39. chain mode without busy indicator connection diagram 06392-024 t conv t cyc t ssdisck t sckl t sck t hsdisc t acq aquisition t ssdicnv aquisition t sckh conversion s do a = sdi b t hsdicnv sck cnv sdi a = 0 sdo b t en d a 15 d a 14 d a 13 d b 15 d b 14 d b 13 d b 1d b 0d a 15 d a 14 d a 0 d a 1 d a 1d a 0 t hsdo 1 2 3 15 16 17 14 18 30 31 32 t dsdo figure 40. chain mode without busy indicator serial interface timing
ad7980 rev. b | page 22 of 28 chain mode with busy indicator this mode can also be used to daisy-chain multiple ad7980s on a 3-wire serial interface while providing a busy indicator. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using three ad7980s is shown in figure 41, and the corresponding timing is given in figure 42. when sdi and cnv are low, sdo is driven low. with sck high, a rising edge on cnv initiates a conversion, selects the chain mode, and enables the busy indicator feature. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when all adcs in the chain have completed their conversions, the sdo pin of the adc closest to the digital host (see the ad7980 adc labeled c in figure 41) is driven high. this transition on sdo can be used as a busy indicator to trigger the data readback controlled by the digital host. the ad7980 then enters the acquisition phase and powers down. the data bits stored in the internal shift register are clocked out, msb first, by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 16 n + 1 clocks are required to readback the n adcs. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate and, consequently, more ad7980s in the chain, provided the digital host has an acceptable hold time. 06392-025 ad7980 c sdo sdi data in irq digital host convert clk cnv sck ad7980 b sdo sdi cnv sck ad7980 a sdo sdi cnv sck figure 41. chain mode with bu sy indicator connection diagram 06392-026 t conv t cyc t ssdisck t sckh t sck t hsdisc t acq t dsdosdi t dsdosdi t dsdodsi aquisition t ssdicnv aquisition t sckl conversion t hsdicnv sck cnv = sdi a sdo a = sdi b sdo b = sdi c sdo c t en d a 15 d a 14 d a 13 d b 15 d b 14 d b 13 d c 15 d c 14 d c 13 d b 1d b 0d a 15 d a 14 d a 1d a 0 d c 1d c 0d b 15 d b 14 d a 0 d a 1 d b 0 d b 1d a 14 d a 15 d a 1d a 0 t hsdo 123 151617 4 1819 3132333435 474849 t dsdo t dsdosdi t dsdosdi figure 42. chain mode with busy indicator serial interface timing
ad7980 rev. b | page 23 of 28 application hints layout the printed circuit board (pcb) that houses the ad7980 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. the pinout of the ad7980, with all its analog signals on the left side and all its digital signals on the right side, eases this task. avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the ad7980 is used as a shield. fast switching signals, such as cnv or clocks, should never run near analog signal paths. crossover of digital and analog signals should be avoided. at least one ground plane should be used. it can be common or split between the digital and analog section. in the latter case, the planes should be joined underneath the ad7980s. the ad7980 voltage reference input ref has a dynamic input impedance and should be decoupled with minimal parasitic inductances. this is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the ref and gnd pins and connecting them with wide, low impedance traces. finally, the power supplies vdd and vio of the ad7980 should be decoupled with ceramic capacitors, typically 100 nf, placed close to the ad7980 and connected using short and wide traces to provide low impedance paths and reduce the effect of glitches on the power supply lines. an example of a layout following these rules is shown in figure 43 and figure 44. evaluating the performance of the ad7980 other recommended layouts for the ad7980 are outlined in the documentation of the evaluation board for the ad7980 (eval-ad7980-cb). the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the eval-control brd3. 0 6392-028 ad7980 figure 43. example layout of the ad7980 (top layer) 0 6392-027 figure 44. example layout of the ad7980 (bottom layer)
ad7980 rev. b | page 24 of 28 outline dimensions compliant to jedec standards mo-187-ba 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.05 0.33 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc pin 1 coplanarity 0.10 3.10 3.00 2.90 3.10 3.00 2.90 5.15 4.90 4.65 figure 45.10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters 031208-b top view 10 1 6 5 0.30 0.23 0.18 * exposed pad (bottom view) pin 1 index area 3.00 bsc sq seating plane 0.80 0.75 0.70 0.20 ref 0.05 max 0.02 nom 0.80 max 0.55 nom 1.74 1.64 1.49 2.48 2.38 2.23 0.50 0.40 0.30 0.50 bsc p i n 1 i n d i c a t o r ( r 0 . 2 0 ) * paddle connected to gnd. this connection is not required to meet the electrical performances . figure 46. 10-lead lead frame chip scale package [qfn (lfcsp_wd)] 3 mm 3 mm body, very very thin, dual lead (cp-10-9) dimensions shown in millimeters contact sales for the non-rohs compliant version of the part.
ad7980 rev. b | page 25 of 28 ordering guide model integral nonlinearity temperature range ordering quantity package description package option branding ad7980armz 1 2.5 lsb max ?40c to +125c tube, 50 10-lead msop rm-10 c5x ad7980armzrl7 1 2.5 lsb max ?40c to +125c reel, 1,000 10-lead msop rm-10 c5x ad7980brmz 1 1.25 lsb max ?40c to +125c tube, 50 10-lead msop rm-10 c5d AD7980BRMZRL7 1 1.25 lsb max ?40c to +125c reel, 1,000 10-lead msop rm-10 c5d ad7980acpz-rl 1 2.5 lsb max ?40c to +125c reel, 5,000 10-lead qfn (lfcsp_wd) cp-10-9 c5x ad7980acpz-rl7 1 2.5 lsb max ?40c to +125c reel, 1,000 10-lead qfn (lfcsp_wd) cp-10-9 c5x ad7980bcpz-rl 1 1.25 lsb max ?40c to +125c reel, 5,000 10-lead qfn (lfcsp_wd) cp-10-9 c5d ad7980bcpz-rl7 1 1.25 lsb max ?40c to +125c reel, 1,000 10-lead qfn (lfcsp_wd) cp-10-9 c5d ad7980bcpz-r2 1 1.25 lsb max ?40c to +125c reel, 1,000 10-lead qfn (lfcsp_wd) cp-10-9 c5d eval-ad7980cbz 1, 2 evaluation board eval-control brd 3 controller board 1 z = rohs compliant part. 2 this board can be used as a standalone evaluation board or in conjunction with the eval-control brd3 for evaluation/demonstrat ion purposes. 3 this board allows a pc to control and communicate with all analog devices evaluation boards ending in the cb designator.
ad7980 rev. b | page 26 of 28 notes
ad7980 rev. b | page 27 of 28 notes
ad7980 rev. b | page 28 of 28 notes ?2007C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06392-0-6/09(b)

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